Timescale and Precision in Verilog & System Verilog

General description of timescale is "time allowed for or taken by a process or sequence of event." We can say System Verilog follows the same description of the timescale.

Let's see this from Verilog or System Verilog perspective. First of all `timescale is compiler directive. This compiler directive specifies the time unit and time precision of the design for particular module. Time unit is the unit of measurement for time values for simulation time as well as delay value.

Here we have used two words
simulation time : In one simulation time all event scheduling regions  specified in System verilog LRM file (IEEE std 1800-2012) is simulation time.
Delay value: Delay value specify the time that should be waited before moving forward at some point. For example you want to give 5ns delay before toggling clock signal value.

Time scale compiler directives is declared as follows :

   `timescale time_unit/time_precision

time_unit specifies the time unit of measurement during simulation for your design or test-bench.
time_precision specifies precision of time for time unit. Or in other way minimum time you are able to specify during simulation.

suppose you have specified timescale as follows.

                 `timescale 1 ns / 1 ps

This means in your System Verilog code whenever you specify #1 delay it will be considered as 1 ns delay.And one more thing you can specify the delay of minimum 1 ps = 0.001 ns. So your specified time delay in your design is rounded around 0.001 precision.

Following is some example that indicates how value of the delays are rounded.

         1.1           ns          is considered as    1.1       ns
         1.1234     ns          is considered as    1.123   ns
         1.1119     ns          is considered as    1.112    ns
         1.1123     ns          is considered as     1.112    ns

You can see that whatever the precision you specify your delay will get rounded around that value only. Neared time delay of 1.1113 in term of ps is 1.112 ns so it is rounded to that value.

Same way we have specified some timescale directives as follows.

`timescale 10ns / 1ns

In this timescale #2 will end up in 20 ns of delay. And you will be able to specify minimum 1ns of delay so #0.1 will give you 1ns of delay.

`timescale 0.001 ns / 1ps 

We can specify same timescale as  : `timescale 1ps / 1ps. 

Effect of Timescale

We have seen how to specify timescale. But what will be effect of the time scale ?? It is really important question as sometimes it happens that you spend 2 hours on debugging something event detection and after that you successfully find out that You have used wrong timescale for your module or package.

It is quite possible that in your top module (which is normally named as top ) you have specified timescale as 1ns / 1ns and in your design you are writing some delay like #25ps. In this case your compiler will count this as #0 ns only and you will not get this delay. That will end up in unspecified behavior of your design or System Verilog testbench.

It is also possible that you miss some pulse detection if it last for less time than your design or System Verilog testbench resolution. For example you have specified timescale as follows.

   `timescale 100ns / 10ns 

And you are getting some signal which is driven by other design which has different time scale with maximum value of resolution 1ns. This signal gives pulse signal which lasts for only one nano second only. So for our design it is quit possible that we miss that pulse and will end up in debugging everywhere in our design or System Verilog testbench.