Friday 26 January 2018

Run VCS simulation in ucli mode

ucli mode is same as -do mode in questa simulation. commands used while running simulation can be. Commands that we are going to discuss below should be stored in .tcl file and run while simulation.

command to be executed after simv run:
 run 

Run simulation VCS simulation with dump:
vcs.fsdb dump file is created. $fsdbDumpvars & +all indicates it will dump all hierarchies. There are many features that ucli mode supports.

call {$fsdbDumpfile ("vcs.fsdb")};
call {$fsdbDumpvars ("+all")};

run 
exit

Run simulation for specific simulation time, following command will run simulation for 100 nano second:
run 100ns 
user can give ps - pico second, us - micro second , ms - milli second 

Run for signal or event:
  - run simulation till first posedge of the ack signal is detected.
run -posdege top.m1.ack

same way we can wait for negedge or change in ack signal.

Thursday 25 January 2018

Bind a module in RTL

Sometimes Designer or Verification engineer do not want to touch design module while implementing assertions of RTL module.

In such cases we can use binding feature of System Verilog.
Binding a module or interface is like instantiating independently defined verification component in RTL.

Lets take an example of AXI Master RTL verification using assertion module.

Code for AXI module:

module AXI_master();
  output [31:0] AWADDR;
  output [2:0]   AWSIZE;
   ...
   ...
   ...
endmodule

Code for the AXI assertions:
module AXI_master_assertions();
  output [31:0] AWADDR;
  output [2:0]   AWSIZE;
   ...
   ...
   ...
  ASSRTION_1
endmodule

Now to bind assertions in AXI_master instance, use following syntax.
bind AXI_master AXI_master_assertions assertion_instance (.*);
.* should be used only if signal names are exactly same in both instance.

If signal names does not match use following syntax.(I would recommend below approach for all cases even if signal names are same)
  
     bind AXI_master AXI_master_assertions assertion_instance (
                          .AWADDR(awaddr),
                          .AWSIZE(awsize)
        );
 
Notes :
  • Binding module is equivalent to taking instance. So car must be taken while using parameter in module instantiation. 
  • Only static components like modules, interface or compilation unit scope can be used. Class or structure can not be bound.