Defining sequece for Assertion in System Verilog

Sequences works on clock ticks. This clock is define as events. In this post we will discuss something that would describe how to write sequential behaviour.

       a ##N b

- when a is true after exactly Nth clock ticks if b is true than sequence evaluates to true. Or we can say after delay of N clock b must be true.

Concatenate any sequence

 

(a ##1 b ##1 c) ##0 (d ##1 e ##1 f)

This seq indicates that once a is true after one clock cycle b is true and after one clock cycle c is true and at the same clock cycle second cycle starts and for that d should be true so ultimately  we can write the whole sequence as follows.

(a ##1 b ##1 c&d ##1 e ##1 f)

Up till now we have seen only linear sequence in which is written simply by specifying exact clock ticks between two events. But what if we have some cases when when delay is not fixed but finite clock ticks. Suppose we want to write sequence in which req is asserted at clock tick nth clock tick and after that in minimum 1 and maximum 5 clock ticks grant is being asserted. One way of doing this is write sequence as follows :

           (a ##1 b) or  (a ##2 b) or  (a ##3 b) or  (a ##4 b) or  (a ##5 b)

But what is there is delay of 5 to 100 clock ticks. If we write this 96 times that is completely absurd. In sequence we have [* repetition operator. The above sequence can be written as follows.

         a ##[1:5] b

Same way if you want to specify min_clk_ticks and max_clk_tiks it can be done as follows.

         a ##[min_clk_ticks:max_clk_ticks] b

If you want to specify min_clk_ticks to any clock tick before end of simulation it is specified by operator $. And expression for this as follows.

         a ##[min_clk_ticks:$] b

This expression indicates that when a is true b must be true any clock ticks after Nth clock ticks.

Goto repetition  [-> & Non-consecutive repetition  [=

Suppose we want to check that particular condition a should remain true for 10 consecutive clock cycle and after that b remains true for consecutive 2 clock cycle and that c is triggered to true. This sequence can be written as follows.

  a ##1 a ##1 a ##1 a ##1 a ##1 a ##1 a ##1 a ##1 a ##1 a ##1 a ##1 a ##1 a ##1 b ##1 b ##1 b ##1 c

But this is not comfortable if we are dealing with 100 clock ticks or 200 clock ticks. Right??

For this System Verilog provides us repetition operator for consecutive matches [* . The above sequence can be written as follows.

                  a ##[*10]  ##1 b ##[*3] ##1 c

We can specify the range of the repetition same way we have seen in previous post. For example :

                  b ##1 a[*0:2] ##2 c

This sequence indicates once b is true a should be true for either 0 times or 1 time  or  2 times and once a is true c should be true after two clock cycles. So, above sequence can be written as follows.

                  (b ##2 c) or (b ##1 a ##2 c) or (b ##2 a ##c)

Using repetition operator we can repeat some particular sequences also and combine it to trigger one seq. For example,

                              (a ##2 b) [*5]

This sequence is  same as

                     (a ##2 b ##1 a ##2 b ##1 a ##2 b ##1 a ##2 b ##1 a ##2 b)

To understand goto repetition we would consider simple example as follows. Let’s take an example of the following seq,

        a ##1 b [->4] ##1 c

This sequence indicates that after a is true b must be true four times with no gap between b and c. So this sequence says that when b is true 4th time it should be penultimate clock cycle of c is true.

         a ##1 ((!b[*0:$] ##1 b) [*4]) ##1 c

Non-consecutive repetition is same as goto repetition. The only difference is that it is not compulsory to be it in penultimate clock cycle.

             a ##1 b [=>4] ##1 c

This sequence indicates that after a is true b must be true four times with gap or no-gap between b and c. So this sequence says that when b is true 4th time it not necessary to be on penultimate clock cycle of c is true.

              a ##1 ((!b[*0:$] ##1 b) [*4]) ##1 !b[*0:$]  ##1 c