Bind a module in RTL

Sometimes Designer or Verification engineer do not want to touch design module while implementing assertions of RTL module.

In such cases we can use binding feature of System Verilog.
Binding a module or interface is like instantiating independently defined verification component in RTL.

Lets take an example of AXI Master RTL verification using assertion module.

Code for AXI module:

module AXI_master();
  output [31:0] AWADDR;
  output [2:0]   AWSIZE;
   ...
   ...
   ...
endmodule

Code for the AXI assertions:
module AXI_master_assertions();
  output [31:0] AWADDR;
  output [2:0]   AWSIZE;
   ...
   ...
   ...
  ASSRTION_1
endmodule

Now to bind assertions in AXI_master instance, use following syntax.

bind AXI_master AXI_master_assertions assertion_instance (.*);

.* should be used only if signal names are exactly same in both instance.

If signal names does not match use following syntax.(I would recommend below approach for all cases even if signal names are same)
  
     bind AXI_master AXI_master_assertions assertion_instance (
                          .AWADDR(awaddr),
                          .AWSIZE(awsize)
        );
 
Notes :

• Binding module is equivalent to taking instance. So car must be taken while using parameter in module instantiation. 
• Only static components like modules, interface or compilation unit scope can be used. Class or structure can not be bound.